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(parent: cdf1da9) | patch
x86/MCE: add more strict sanity check of one SRAR case
authorLiu, Jinsong <jinsong.liu@intel.com>
Thu, 15 Dec 2011 09:58:53 +0000 (10:58 +0100)
committerLiu, Jinsong <jinsong.liu@intel.com>
Thu, 15 Dec 2011 09:58:53 +0000 (10:58 +0100)
commit1cf8a44e39c5b21cfe67ddb61fe2b91b807443c6
treedb6c9542e22f491db498fbb43fecb720a6368ec9tree | snapshot
parentcdf1da9433e0ddf3345fc5a04840b0171d8f0f0ecommit | diff
x86/MCE: add more strict sanity check of one SRAR case

When RIPV = EIPV = 0, it's a little bit tricky. It may be an asynchronic error, currently we have no way to precisely locate whether the error occur at guest or hypervisor.
To avoid handling error in wrong way, we treat it as unrecovered.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/mcheck/mce_intel.c diff | blob | history
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